Announcement PDF AI & Semiconductors: ASX-Listed Stocks Investor Webinar Adisyn Ltd (ASX:AI1) 22 September 2026 2 Disclaimer This information contained in this presentation has been prepared by Adisyn Ltd (ACN 155 473 304) (ASX:AI1 or ‘the Company’) and makes statements about it as well as its subsidiaries, the presentation is for information purposes only. This presentation does not constitute financial product or investment advice or a recommendation to acquire AI1 shares and has been prepared without taking into account the objectives, financial situation or needs of individuals. This presentation does not purport to contain all of the information that a prospective investor may require to make an evaluation of the Company or its business activities. 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This presentation has been authorised for release on the ASX by the Board of Directors of AI1. Financial Data. All dollar values are in AUD dollars (AUD or $) and are unaudited (unless otherwise presented). This presentation has been authorised for release on the ASX by the Board of Directors of AI1. Future performance any forward looking statements, opinions and estimates provided in this presentation are based on assumptions and contingencies which are subject to change without notice, as are statements about market and industry trends, which are based on interpretations of current market conditions at the date of this presentation. Forward looking statements including projections, guidance on future earnings and estimates are provided as a general guide only and should not be relied upon as an indication or guarantee of future performance. An investment in AI1 shares is subject to investment and other known and unknown risks, some of which are beyond the control of AI1. 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Such forecasts, prospects or returns are by their nature subject to significant uncertainties and contingencies. 3 Who is Adisyn W HO IS AD I S YN Adisyn Ltd is publicly listed on the Australian Securities Exchange (ASX) under the ticker AI1 01 2D Generation A fully owned subsidiary. Development of novel technologies to produce graphene in a low-temperature process, targeting semiconductors. 2D Radar Absorbers A subsidiary of 2D Generation. Radar signature reduction for UAV and defence systems, using 2D materials. IT and cyber security The original activity of building and deploying IT solutions, and end-to-end cyber security solutions. CORPO RAT E SNAPSHOT Share price, 21/09/26 A$0.14 Market cap, 21/09/26 c. A$165M Cash, 30/06/26 c.A$15.5M BO ARD O F DIRECTO RS Kevin Crofton Executive Chairman Arye Kohavi Non-Executive Director Dominic O’Hanlon Non-Executive Director Blake Burton Executive Director 02 03 (ASX:AI1) 4 Semiconductor $1T Milestone Accelerated T H E M A R K E T $1.0T Milestone crossed The industry passes one trillion dollars this decade. $1.5T By 2030 (F) AI is what pulls the curve above the earlier forecast. SOURCE: TSMC 5 T H E M A R K E T The AI market drives the semiconductor ecosystem $1,157.6 Billion by 2030 Up from $446.7B in 2020. 71.7% AI share by 2030 It was 9.7% in 2020. 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 AI Non-AI Source: IBS, February 2025. In billion $. 9.7% 12.3% 15.8% 22.7% 26.7% 34.2% 42.3% 51.5% 58.1% 65.0% 71.7% $446.7 $547.1 $564.3 $525.4 $622.0 $691.8 $671.4 $841.0 $932.4 $1,037.3 $1,157.6 6 I N T E R F A C E R E S I S T A N C E High Performance Computing’s Primary Barrier Interfaces contributes >50% of resistance >5 interfaces at narrow via-line connections Atomic-level nucleation and termination of interfaces Resistance (R) escalates at small dimensions Higher resistance = higher dynamic power loss >1/3rd of chip power is consumed in 7 W H A T T H E I N D U S T R Y N E E D S Industry Must- Have Solutions To support the coming demands. Requirements for high performance, low power AI semiconductors. High Performance Increasing speed of device 01 Low Power Reducing power consumption 02 High Density Smaller chips or stacked chips, to process more data 03 High Bandwidth Transmission of large amounts of data at once 04 Low Latency Connection pathway of data transmission without delay 05 Five requirements, one constraint They all run into the same interconnect limit. 8 2 D G E N E R A T I O N P R O C E S S <450°C A unique and patented process, compatible with fab constraints Automic Layer Deposition (ALD) based, low- temperature, using readily available precursors, and applicable with existing industrial processes and equipment. Unique and patented process Four patent families sit behind it. Compatible with fab constraints ALD based. Low-temperature, well below 450°C. Uses readily available precursors. Existing industrial equipment Can be applied using industrial processes and equipment that fabs already run. 9 T H E M O A T Expanding IP Coverage Across the Graphene Interconnect Stack AI1 is building an IP position around both the process of depositing graphene and its integration into next- generation semiconductor interconnect structures. Third Patent Extends Adisyn’s Graphene IP into Non-metallic Surfaces • Patents 1 & 2: Cover graphene deposition onto metallic surfaces and resulting metal-based interconnect products. • Patent 3: Extends protection to direct graphene deposition on non-metallic surfaces, including interconnect structures where graphene acts as the diffusion barrier between the conductor and surrounding dielectric (including sidewalls). • Together, the patent portfolio potentially provides IP coverage “across both sides of the barrier interface.” • This creates multiple potential points of IP relevance as the semiconductor industry seeks to integrate graphene into conventional interconnect manufacturing. • Industry validation: imec has investigated graphene as an ultrathin diffusion barrier, highlighting characteristics including atomic-scale thickness, high current-carrying capacity, thermal conductivity and electromigration performance. 10 ~1 nm T H E P R O O F layer of graphene, d = 3.4 ± 0.3 &Aring; Successful Deposition of Continuous Layer Of Graphene at Low Temperature Graphene layers Tungsten protection layer Copper substrate 11 Raman Analysis – Low-temp PEALD Graphene Deposition on Copper Substrate T H E P R O O F The low-temp deposition shows both. The copper reference sample shows neither. 12 August 2026: Scale-up milestone on a 200mm wafer T H E P R O O F Independent tests confirmed graphene across 12 sampled locations. 12 of 12 Sampled locations confirmed 5 Measurements per location 200mm Wafer 13 7.7M(~2M SAM) W H A T T H E 2 0 0 M M R E S U L T M E A N S wafer starts a month, and a path to potential first revenue Around 20 to 30% of that would represent our Serviceable Addressable Market (SAM) for graphene, at potentially lower risk for adoption than leading-edge logic. Scale Immediate indication of potential to scale to 300mm, critical for AI and HPC devices. Specialty device makers Opens the avenue to engage with specialty device makers, with Significant TAM of 7.7M wafer starts per month An economic play Power semiconductors, RF & MEMS, advanced sensors, even potentially analog. • C. 20–30% would represent our SAM for graphene Source: Semi 200MM Fab Outlook Report 14 T H E J O U R N E Y Hitting milestones at increasing velocity Deposition using ALD at below 300°c, well below thermal limit for the semi-industry of ¬450°C January 2026 Demonstration of full graphene coverage on 1cmx1cm coupon, well below 450°C April 2026 Repeatable graphene deposition below 300°C verified by UNSW June 2026 Major graphene scale up to industrial size 200mm semiconductor wafer (300X the 1cm2 coupon). 200mm wafers account for >50% of the market. August 2026 ❖300mm wafer ❖Repeatability and manufacturability testing ❖Commercial partnerships ❖Team buildout What’s Next? 15 T H E M O N E Y Highly Scalable Revenue Model Additional scalable route to market Alongside licensing directly to manufacturers such as TSMC, Samsung or Intel, Adisyn's graphene deposition process could potentially be integrated into semiconductor deposition equipment → reaching multiple foundries and chip customers. From Patent Portfolio → Non-Recurring Engineering Revenue → Low-Rate Production → Industry Adoption → Recurring Royalties Annual wafers using technology Illustrative annual royalty revenue* 1 million US$10m 10 million US$100m 50 million US$500m Illustrative royalty economics — US$10 per wafer *Illustrative only. Not a forecast or indication of expected pricing, adoption or revenue. Approximately 95–105 million 300mm wafers are expected to be produced in 2026, potentially increasing to 130–140 million annually by 2030, which excludes the substantial 200mm wafer market. Source: Semi 300MM Fab Outlook Report Appendix Adisyn Ltd (ASX:AI1) Kevin Crofton investors@adisyn.com David Tasker dtasker@chapteroneadvisors.com.au Michael Shaw-Taylor mst@sandtoncapital.com.au Executive Chair, AI1 IR / PR Corporate Advisor 17 T H E M O A T Intellectual Property 01 Graphene coated non-metallic surfaces, devices and method thereof Directed to the technologies used for conductive diffusion barrier, and other applications. 02 Graphene coated metallic surfaces, devices and method of manufacture thereof Directed to the technologies used for conductive capping layer, and other applications. 03 Method of manufacture of graphene coated surfaces by atomic or molecular layer deposition Directed to graphene manufacture by ALD. 04 Graphene metal composite Directed to graphene layers interlayered with metal layers, including coatings of patterned surfaces. Four patent families covering the interconnect including both sides of the barrier interface. 18 Proven business models used in the semi industry T H E M O D E L Process platform plus running royalty The classic approach, but with the lowest potential revenue. Large paid technology transfer / joint-development programme Long programme, large revenue and very long timelines. For example IBM through the 1990s, 2000s and into the 2010s. Staged licence Evaluation, then R&D, then HVM, then per-wafer or per-device royalty. The model used by Soitec, Atomera and in the ST / Infineon / IBM copper example. 19 Multi-band Radar Systems Detect UAVs Earlier Than Ever The Physical Meaning of 30dB: Reducing Radar Signature by 1,000 Times Before After Standard UAV Decibels are a logarithmic scale and a 30dB reduction can equate to a 1,000x decrease in radar signature. How modern radar systems detect uavs • Transmits a pulse of radio frequencies • The signals hit an object, for example a UAV • Part of the signal is reflected back to the radar receiver • The radar measures the strength of the returned signal Signal strength is expressed in decibels Stealth Butterfly 10 sq cm Only 1 Square Meter 20 The Adisyn Solution T H E S E C O N D L I N E Graphene-enhanced structural components which are light, strong and possess significant radar-absorbing properties. Proof-of-concept result: 20dB reduction, a 100-fold decrease in radar return, successfully achieved in the lab by integrating advanced 2D graphene materials directly into the printed plastic matrix. Ongoing optimisation targeting ~30dB radar signature reduction, which can equate to a 1,000-fold decrease in radar return. This substantially surpasses current conventional products and would permit access to higher-margin markets. Proven 20dB Reduction 20dB with graphene composites compared to base materials Successfully Completed Proven reduction in radar signal return Current Achievement: Thank You Kevin Crofton investors@adisyn.com David Tasker dtasker@chapteroneadvisors.com.au Michael Shaw-Taylor mst@sandtoncapital.com.au Executive Chair, AI1 IR / PR Corporate Advisor Adisyn Ltd (ASX:AI1)